Intel NVM

• Write is significantly lower than DRAM
• DFS (direct file system):
  • use fsync: makes sure the data leaves the memory and goes to the device
  • the sync for NVM needs to make sure that the cache gets flushed
• Multi-threaded programming: lower level compiler must ensure visibility and ordering among threads; caches will do the right thing under the hood
  • Recovery observer: after the power

Commands

• CLFLUSH: cash line flush: evicts the cache
  • no ordering unless you add additional instructions
• SFENCE: store fence
  • protects pieces of code from occurring out of order
  • Note: Intel X86 does not reorder stores with stores or loads with loads. It only reorders loads above stores. Thus SFENCE is not use that frequently.
• LFENCE: with weaker memory models would need to be inserted by the compiler
• CLWB: cache line write back
  • followed by SFENCE

C++ Modes of Ordering

• the default is full fencing but can be relaxed
• mfence